1. Field of the Invention
The present invention relates to phase-locked loop (xe2x80x9cPLLxe2x80x9d) circuits, and, more particularly, to a loop filter for a PLL circuit. More specifically, the present invention relates to a low-jitter loop filter for a PLL circuit.
2. Description of Related Art
A phase-locked loop (xe2x80x9cPLLxe2x80x9d) circuit generally includes a phase detector, a loop filter, and a controlled oscillator. The phase detector receives an input signal, which has a reference frequency. The output signal of the controlled oscillator is fed back to the phase detector. The frequency of the output signal is typically a multiple of the reference frequency of the input signal. The PLL circuit is utilized to lock the output frequency to the input frequency. Locking the output frequency to the input reference frequency is critical in various applications, such as developing accurate and precise clocks for digital signal processors (xe2x80x9cDSPsxe2x80x9d) and for audio sampling frequencies and rates. Fast locking applications also exist in which adaptive bandwidth PLLs have been developed and used.
PLL circuits in mixed-signal integrated circuit designs typically operate in noisy environments. Much of the noise is introduced through the current or voltage supplies, the substrate, temperature variations, process parameters, or other such sources. Low jitter PLL circuits require high loop bandwidths to reject the noise.
Passive loop filters for PLL circuit designs are popular due to their simplicity, but the control of their loop time constants lacks flexibility. Active loop filters used in conjunction with feed-forward charge pumps provide a wider range of loop time constants and often provide a decreased area of on-chip capacitance. Fully differential charge pumps for PLL circuit designs have been of great interest due to their ability to reject noise. However, fully differential charge pumps require increased on-chip capacitance and extra circuitry for common mode feedback. One drawback of a charge pump PLL circuit is that setting the loop filter pole position requires a compromise between the loop phase margin and the jitter performance.
Typical charge pump PLL circuits having two poles at the origin require a zero to be introduced in the loop for stability. A common method of adding a zero is to couple a resistor in series with the charge pump capacitor or by using a feed-forward technique. Most charge pump PLLs use a proportional signal that is based on the instantaneous phase difference. The signal in lock is characterized by narrow high amplitude pulses, that even after filtering, lead to an abrupt variation of the oscillator control signal and rapid frequency changes that degrade the jitter performance of the PLL circuit.
With reference now to FIG. 1, an exemplary phase-locked loop (xe2x80x9cPLLxe2x80x9d) circuit 100 according to the prior art is shown. PLL circuit 100 includes a phase frequency detector (xe2x80x9cPFDxe2x80x9d) 104, a charge pump (xe2x80x9cCPxe2x80x9d) 106, a loop filter 108, and a controlled oscillator (xe2x80x9cCOxe2x80x9d) 116 coupled together in series. An N divider 102 is coupled to an input of the PFD 104. An M divider 118 is coupled to the output of the CO 116, and the output of M divider 118 is coupled and fed back to another input of the PFD 104. An input signal 101 is fed into N divider 102 and divides input signal 101 by a factor of N to provide input reference signal 103. The N-divided input reference signal 103 is fed as an input signal into PFD 104. Furthermore, an output signal 120 of PLL circuit 100 is fed into an M divider 118 as shown in FIG. 1. M divider 118 divides output signal 120 by a factor of M to provide an input feedback signal 105.
PFD 104 compares the frequencies or phases of input reference signal 103 and feedback signal 105. PFD 104 generates and outputs a phase error signal to CP 106. The phase error signal is the difference in phase between what the phase of the signal currently is (e.g., phase of feedback signal 105) and what the phase of the signal should be (e.g., phase of the input reference signal 103). The phase error signal may be passed onto loop filter 108 in terms of a current value (e.g., charge stream) from CP 106. Loop filter 108 filters currents from CP 106 by passing some current signals at certain frequencies while attenuating other current signals at other frequencies. Loop filter 108 provides and outputs a control signal to tune the phase of the output signal 120 based on any difference between the control signal and a normal operating or optimum signal. The control signal is input into CO 116 to provide an output phase for output signal 120 that the loop will lock with the reference phase of input reference frequency 101.
Loop filter 108, which is an exemplary loop filter according to the prior art, has a proportional signal path 107 and an integral signal path 109. Proportional signal path 107 includes a resistor 110 having one node coupled to the output of CP 106 and the other node coupled in series to a node of a proportional path capacitor 112. The other node of proportional path capacitor 112 is coupled to ground. Integral signal path 109 includes an integral path capacitor 114. One node of integral path capacitor 114 is also coupled to the output of CP 106, and the other node of integral path capacitor 114 is coupled to ground. Proportional signal path 107 generates a proportional signal that is based on the instantaneous phase difference. Integral signal path 109 provides an integral signal, which tracks the overall input signal level that includes past proportional input signals. Loop filter 108 generates and outputs the control signal, which is the sum of the present proportional signal with the overall signal level, to CO 116. CO 116, in turn, generates output signal 120 having an output phase that the loop will lock with the reference phase of input reference frequency 103.
Referring now to FIG. 2, an exemplary graph 200 showing ideal signals or pulses 206, 208, and 210 generated by proportional path 107 of loop filter 108 according to the prior art is depicted. In exemplary graph 200, proportional path signal 202 is plotted against time 204. When PFD 104 of PLL circuit 100 detects instantaneous phase differences, proportional path 107 of loop filter 108 outputs pulses 206, 208, and 210 to CO 116. Pulses 206, 208, and 210 vary in width based on the magnitudes of the detected phase differences (e.g., from larger to smaller pulses based on respective larger to smaller magnitudes of phase differences). As shown in FIG. 2, pulses 206, 208, and 210 occur in the early portions of update periods (xe2x80x9cTupdatesxe2x80x9d) 205. The signal levels then return to a zero level for the remaining portions of Tupdates 205.
As stated earlier, pulses 206, 208, and 210 based on instantaneous phase differences lead to abrupt variations of the signal of CO 116 and rapid frequency changes that degrade the jitter performance of PLL circuit 100. With reference now to FIG. 3, an exemplary graph 300 illustrating the input signal to CO 116 from loop filter 108 according to the prior art is depicted. In exemplary graph 300, CO input signal 302 is plotted against time 304. Exemplary graph 300 shows integral path signal 308 plotted against time 304. Integral path signal 308 only sums the past pulses but is not substantially affected by any single pulse 206, 208, or 210 of proportional path 107. Exemplary graph 300 further shows proportional path signal 310 and the total CO input signal 306 having waveforms with jitter that is attributed to pulses similar to pulses 206, 208, and 210 of proportional path 107. The jitter occurs both in the unlocked and locked periods of PLL circuit 100. As shown in FIG. 3, the pulses therefore negatively affect the overall jitter performance of PLL circuit 100.
It is well known in the art that signals for a PLL circuit can be either voltage signals or current signals. Conversion between the voltage and current domains can be performed. Therefore, a PLL circuit could be described as a system having either a respective voltage or current mode filter and either a respective voltage or current controlled oscillator.
The present invention recognizes the desire and need for reducing the jitter in a PLL circuit. The present invention further recognizes the desire and need to eliminate or minimize the effects of the current pulses generated by the proportional path of a PLL loop filter. The present invention also recognizes the desire and need not to compromise loop phase margin for a PLL circuit and to provide and maintain stability for a PLL circuit. The present invention overcomes the problems and disadvantages in accordance with the prior art.
A loop filter device and method for a phase locked loop (xe2x80x9cPLLxe2x80x9d) circuit, which locks a frequency of a signal to a reference frequency, are disclosed. The loop filter includes a proportional path circuit and an integral path circuit. The proportional path circuit receives a charge pump output and determines and holds a charge to be directed to or taken from the PLL circuit throughout an update period based on a detected phase difference for the update period for locking a frequency of a signal for the PLL circuit to a reference frequency. The integral path circuit is coupled to the proportional path circuit, and the integral path circuit receives another charge pump output and tracks a total charge level for the PLL circuit based on phase differences for present and prior update periods.
An object and advantage of the present invention is to provide a loop filter having an integral path circuit and a proportional path circuit, which receives a charge pump output and determines and holds a charge to be directed to or taken from the PLL circuit throughout an update period based on a detected phase difference for the update period for locking a frequency of a signal for the PLL circuit to a reference frequency.
An aspect and advantage of the present invention is to provide the loop filter device and method in which a transconductance stage of the proportional path circuit receives as an input the charge pump output for converting a voltage signal based on the signal for the PLL circuit to a current signal. A capacitor is coupled between the input of the transconductance stage and a reset voltage level. The capacitor is able to be charged to hold the charge and to be reset by discharging to the reset voltage level. Another capacitor is coupled between the input of the transconductance stage and the reset voltage level. The other capacitor is also able to be charged to hold the charge and to be reset by discharging to the reset voltage level.
Another aspect and advantage of the present invention is to provide the loop filter device and method in which the proportional path circuit activates a hold switch to couple the capacitor to one charge pump. The proportional path circuit activates a reset switch to couple the capacitor to a reset voltage source to set the capacitor to the reset voltage level and activates another hold switch to couple the other capacitor to the one charge pump. The proportional path circuit activates another reset switch to couple the other capacitor to the reset voltage source to set the other capacitor to the reset voltage level.
A further aspect and advantage of the present invention is to provide the loop filter to which a phase detector that measures the phase difference and controls activation and deactivation of the hold switch, the reset switch, the other hold switch, and the other reset switch to charge, hold, and reset the capacitor and the other capacitor at appropriate times.
A still further aspect and advantage of the present invention is to provide the loop filter device and method in which the charge of the capacitor is reset. The phase frequency detector detects a beginning edge of the phase difference and deactivates the hold switch and the reset switch to couple the capacitor to the one charge pump to set the capacitor with the charge. The phase frequency detector detects a finishing edge of the phase difference. The phase frequency detector activates the hold switch to hold the capacitor with the charge and maintains the reset switch as deactivated so that the capacitor is coupled between the input of the transconductance stage and the reset voltage level. The phase frequency detector further deactivates another hold switch and activates another reset switch to couple the other capacitor to the reset voltage source to set another capacitor to the reset voltage level and to uncouple the other capacitor from the one charge pump. The phase frequency detector maintains the charge of the capacitor until the phase frequency detector detects a next phase difference.
Still another aspect and advantage of the present invention is to provide the loop filter device and method in which the phase frequency detector detects a beginning edge of the next phase difference. The phase frequency detector maintains the other hold switch as deactivated and deactivates the other reset switch to couple the other capacitor to the one charge pump to set the other capacitor with the charge. The phase frequency detector detects a finishing edge of the next phase difference and activates the other hold switch to hold the other capacitor with the charge. The phase frequency detector maintains the other reset switch as deactivated so that the other capacitor is coupled between the input of the transconductance stage and the reset voltage level. The phase frequency detector further deactivates the hold switch and activates the reset switch to couple the capacitor to the reset voltage source to set the capacitor to the discharged voltage level and to uncouple the capacitor from the one charge pump. The phase frequency detector maintains the charge of the other capacitor until the phase frequency detector detects a following phase difference.
A further aspect and advantage of the present invention is to provide the loop filter device and method in which the phase frequency detector repeats the operations of charging, holding, and resetting of the capacitor and the other capacitor for future phase differences detected by the phase frequency detector.
Another object and advantage of the present invention is to provide a phase-locked loop circuit and method for locking a frequency of a signal to a reference frequency which includes, incorporates, and implements the above-referenced loop filter. The PLL circuit has a phase frequency detector, the above-indicated loop filter, a current adder, and a current-controlled oscillator coupled together in series. The phase frequency detector receives as input signals a reference frequency signal and a fed back output signal of the current-controlled oscillator.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.